The present invention relates in general to data processing systems, and in particular, to an arithmetic logic circuitry for performing a floating point arithmetic add/subtract operation in decimal or binary floating point format.
The “IEEE-754R Standard for Binary Floating point Arithmetic” specifies a floating point data architecture that is commonly implemented in computer hardware, such as floating point processors having multipliers. The format consists of a sign, an unsigned biased exponent, and a significand. The sign bit is a single bit and is represented by an “S”. The unsigned biased exponent, represented by an “e,” is e.g. 8 bits long for single precision, 11 bits long for double precision and 15 bits long for quad precision. The significand is e.g. 24 bits long for single precision, 53 bits long for double precision and 112 bits long for quad precision.
Decimal floating point has been used in calculators for many years but the latest revision of the IEEE standard for floating point numbers, IEEE-754R, includes a decimal floating point format. Addition and subtraction are the primary arithmetic instructions and they are critical to the performance of a decimal floating point unit. Floating point arithmetic is more complex than fixed point arithmetic due to the requirement to align the operations. Decimal floating point formats, as defined by the IEEE 754R standard, include a double word format containing sixteen digits for the coefficient and a quad word format containing thirty-four digits for the coefficient. The coefficients are integer and are not normalized and therefore, can contain leading zeroes. With the advent of the new standard and the increase of financial workloads that rely on decimal arithmetic operations, it becomes desirable to implement these operations at a high performance.
U.S. Pat. No. 8,161,091 B2 discloses a system for performing a decimal floating point operation. The system includes an adder, a final result selector, and a mechanism for receiving a first operand including a first coefficient and a first exponent. The mechanism also receives a second operand including a second coefficient and a second exponent. An operation associated with the first operand and the second operand is received, where the operation is an addition or a subtraction. Three concurrent calculations are performed on the first operand and the second operand. The first concurrent calculation includes applying the operation to the first operand and the second operand based on a first assumption that the first exponent is equal to the second exponent. Then applying the operation based on the first assumption results in a first result and includes utilizing the adder. The second concurrent calculation includes applying the operation to the first operand and the second operand based on a second assumption that an absolute difference between the first exponent and the second exponent is less than or equal to a number of leading zeroes in the larger of the first operand and the second operand. Then applying the operation based on the second assumption results in a second result and includes utilizing the adder. The third concurrent calculation includes applying the operation to the first operand and the second operand based on a third assumption that the absolute difference between the first exponent and the second exponent is greater than the number of leading zeroes in the larger of the first operand and the second operand. Then applying the operation based on the third assumption results in a third result and includes utilizing the adder. A final result is selected by the final result selector from the first result, the second result and the third result.